This invention relates to the field of integrated circuit fabrication. More particularly, this invention relates to a process of forming a composite barrier layer including a diamond film for low-k dielectric interconnects.
As integrated circuits become more complex, it becomes necessary to develop new structures and fabrication techniques which tend to minimize the overall size of the integrated circuits. One technique for reducing the physical size of an integrated circuit is to form multi layered structures where metallic interconnects, separated by interlevel dielectric layers, define various electrical pathways. As the size of the circuit is reduced, electrical contacts, such as via holes and other structures, tend to be smaller and disposed in closer proximity to one another.
A typical integrated circuit fabrication process uses a barrier layer between the substrate and electrical interconnection conduction layers. After depositing the barrier layer, a seed layer is typically deposited. Finally, the conduction layer is deposited over the seed layer, followed by chemical mechanical or electro polishing of the various layers.
Often, the barrier layers do not provide adequate protection from diffusion of the material of the conduction layer or other layers into the material of the substrate. Such diffusion tends to corrupt the operation of the integrated circuit formed in the substrate. As the trend toward fabrication of devices having smaller feature sizes and higher performance continues, better materials and processes must be used to avoid fabrication problems such as that describe above. The careful selection of proper materials can achieve both better device performance and minimize production costs by improving the device yield during manufacturing.
What is needed, therefore, is a method for forming a barrier layer that more fully inhibits the material of the conduction layer or other layers from diffusing into unintended areas of the substrate.
The above and other needs are met by a method of forming an electrically conductive interconnect on a substrate. An interconnection feature is formed on the substrate, and a first barrier layer is deposited on the substrate. The first barrier layer consists essentially of a diamond film. A seed layer consisting essentially of copper is deposited on the substrate, and a conductive layer consisting essentially of copper is deposited on the substrate. Thus, by using a diamond film as the barrier layer, diffusion of the copper from the conductive layer into the material of the substrate is substantially reduced and preferably eliminated.
In various preferred embodiments, a second barrier layer is deposited on the substrate prior to depositing the seed layer. The first barrier layer of diamond and the second barrier layer define a composite barrier layer. Most preferably the second barrier layer is at least one of tantalum, tantalum nitride, tungsten nitride, and titanium silicon nitride. The second barrier layer may, in various embodiments, be deposited using either a chemical vapor deposition process or physical vapor deposition process.
Preferably, the electrically conductive interconnect is planarized to a level substantially planar with a top surface of the substrate, most preferably with a chemical mechanical polishing process.
In another aspect of the invention an integrated circuit is described, which integrated circuit includes an electrically conductive interconnect formed according to the method as described above.